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Rev 1; 9/05
3.3V Center Spread-Spectrum EconOscillatorTM
General Description
The DS1089L is a clock generator that produces a spread spectrum (dithered) square-wave output of frequencies from 130kHz to 66.6MHz. The DS1089L is shipped from the factory programmed at a specific frequency. The DS1089L is pin-for-pin compatible with the DS1087L, however, the DS1089L dithers at equal percentages above and below the center frequency. The user still has access to the internal frequency divider, selectable 1%, 2%, 4%, or 8% dithered output, dithering rate, and programmable output powerdown/disable mode through an I2CTM-compatible programming interface. All the device settings are stored in nonvolatile (NV) EEPROM allowing it to operate in stand-alone applications. The DS1089L also has power-down and output-enable control pins for powersensitive applications.
Features
Factory-Programmed Square-Wave Generator from 33.3MHz to 66.6MHz Center Frequency Remains Constant Independent of Dither Percentage No External Timing Components Required EMI Reduction Variable Dither Frequency User Programmable Down to 130kHz with Divider (Dependent on Master Oscillator Frequency) 1%, 2%, 4%, or 8% Selectable Dithered Output Glitchless Output-Enable Control I2C-Compatible Serial Interface Nonvolatile Settings Power-Down Mode Programmable Output Power-Down/Disable Mode
DS1089L
Applications
Automotive Infotainment Printers Copiers Computer Peripherals POS Terminals Cable Modems
Ordering Information
PART DS1089LU-yxx* TEMP RANGE -40C to +85C PIN-PACKAGE 8 SOP (118 mil)
*See Standard Frequency Options Table.
Pin Configuration and Typical Operating Circuits appear at end of data sheet.
Standard Frequency Options
PART DS1089LU-21G DS1089LU-4CL DS1089LU-22F DS1089LU-23C DS1089LU-450 DS1089LU-866 DS1089LU-yxx FREQUENCY (MHz) 14.7456 18.432 24.576 33.3 50.0 66.6 Fixed up to 66.6 SPREAD (%) 1 2 1 1 2 4 1, 2, 4, or 8 DITHER FREQUENCY fMOSC / 4096 fMOSC / 4096 fMOSC / 2048 fMOSC / 4096 fMOSC / 4096 fMOSC / 4096 fMOSC / 2048 or 4096 or 8192
Add "/T" for Tape and Reel. Custom frequencies available, contact factory.
EconOscillator is a trademark of Dallas Semiconductor Corp. I2C is a trademark of Philips Corp. Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
3.3V Center Spread-Spectrum EconOscillatorTM DS1089L
ABSOLUTE MAXIMUM RATINGS
Voltage on VCC Relative to Ground.......................-0.5V to +6.0V Voltage on SPRD, PDN, OE, SDA, SCL Relative to Ground* ........................-0.5V to (VCC + 0.5V) Operating Temperature Range ...........................-40C to +85C *This voltage must not exceed 6.0V.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Programming Temperature Range .........................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature...................See IPC/JEDEC J-STD-020A
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +85C)
PARAMETER Supply Voltage High-Level Input Voltage (SDA, SCL, SPRD, PDN, OE) Low-Level Input Voltage (SDA, SCL, SPRD, PDN, OE) SYMBOL VCC VIH VIL (Note 1) CONDITION MIN 2.7 0.7 x VCC -0.3 TYP 3.3 MAX 3.6 VCC + 0.3 0.3 x VCC UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +3.6V, TA = -40C to +85C)
PARAMETER High-Level Output Voltage (OUT) Low-Level Output Voltage (OUT) Low-Level Output Voltage (SDA) High-Level Input Current Low-Level Input Current Supply Current (Active) Standby Current (Power-Down) SYMBOL VOH VOL VOL1 VOL2 IIH IIL ICC ICCQ IOL = 4mA 3mA sink current 6mA sink current VIH = VCC VIL = 0V CL = 15pF, fOUT = fMOSCmax Power-down mode -1 12 10 CONDITION IOH = -4mA, VCC = min MIN 2.4 0.4 0.4 0.6 1 TYP MAX UNITS V V V A A mA A
2
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3.3V Center Spread-Spectrum EconOscillatorTM
MASTER OSCILLATOR CHARACTERISTICS
(VCC = +2.7V to +3.6V, TA = -40C to +85C)
PARAMETER Internal Master Oscillator Frequency Master Oscillator Frequency Tolerance Voltage Frequency Variation Temperature Frequency Variation (Note 4) SYMBOL fMOSC CONDITION MIN 33.3 VCC = 3.3V, TA = +25C (Note 2) TA = +25C (Note 3) VCC = 3.3V, fOUT = fMOSCmax J3 = J2 = GND Dither Frequency Range (Note 5) J3 = GND, J2 = VCC J3 = VCC, J2 = GND J3 = J2 = VCC Dither Frequency (Note 5) J1 = GND, J0 = VCC fMOD J1 = VCC, J0 = GND J1 = J0 = VCC TA = 0C to +85C TA = -40C to 0C TYP MAX 66.6 UNITS MHz
DS1089L
fMOSC fMOSC f fMOSC f fMOSC
-0. 5
+0. 5
%
-0.75 -0.75 -2.00 1 2 4 8 fMOSC / 2048 fMOSC / 4096 fMOSC / 8192
+0.75 +0.75
%
% +0.75
%
Hz
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +3.6V, TA = -40C to +85C)
PARAMETER Frequency Stable After PRESCALER Change Power-Up Time Enable of OUT After Exiting Power-Down Mode OUT Disabled After Entering Power-Down Mode Load Capacitance Output Duty Cycle (fOUT) tPOR + tSTAB tSTAB tPDN CL (Note 6) (Note 6) 7 15 50 50 40 SYMBOL CONDITION MIN TYP MAX 1 200 512 UNITS Period s clock cycles s pF %
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3
3.3V Center Spread-Spectrum EconOscillatorTM DS1089L
AC ELECTRICAL CHARACTERISTICS--I2C INTERFACE
(VCC = +2.7V to +3.6V, TA = -40C to +85C, unless otherwise noted. Timing referenced to VIL(MAX) and VIH(MIN).)
PARAMETER SCL Clock Frequency Bus Free Time Between Stop and Start Conditions Hold Time (Repeated) Start Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time Start Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Setup Time SDA and SCL Capacitive Loading EEPROM Write Time SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB tWR (Note 8) (Note 9) 10 (Note 8) (Note 8) (Note 7) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 20 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF ms
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.7V to +3.6V)
PARAMETER Writes SYMBOL +70C CONDITION MIN 10,000 TYP MAX UNITS
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
Note 7: Note 8: Note 9:
All voltages are referenced to ground. This is the absolute accuracy of the master oscillator frequency at the default settings with spread disabled. This is the change that is observed in master oscillator frequency with changes in voltage at TA = +25C. This is the change that is observed in master oscillator frequency with changes in temperature at VCC = 3.3V. The dither deviation of the master oscillator frequency is biderectional and results in an output frequency centered at the undithered frequency. This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally introduced to allow the oscillator to stabilize. tSTAB is equivalent to 512 master clock cycles and will depend on the programmed master oscillator frequency. Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing. CB--total capacitance of one bus line in picofarads. EEPROM write time applies to all the EEPROM memory and SRAM shadowed EEPROM memory when WC = 0. The EEPROM write time begins after a stop condition occurs.
4
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3.3V Center Spread-Spectrum EconOscillatorTM DS1089L
Typical Operating Characteristics
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS 1089L toc01
ACTIVE SUPPLY CURRENT vs. TEMPERATURE
DS 1089L toc02
SUPPLY CURRENT vs. PRESCALER
TA = +25C, fMOSC = 50MHz, OUTPUT UNLOADED
DS 1089L toc03
10 TA = +25C, OUTPUT UNLOADED 66MHz
10 9 8 SUPPLY CURRENT (mA) 7 6 5 4 3 2 1 33MHz 50MHz 130kHz TA = +25C, OUTPUT UNLOADED 66MHz
10
8 SUPPLY CURRENT (mA)
8 SUPPLY CURRENT (mA)
6
6
4 33MHz
50MHz
130kHz
4 3.6V 3.3V 2.7V 1 10 100 1000
2
2
0 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
0 PRESCALE DIVIDER (DECIMAL)
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
DS 1089L toc04
FREQUENCY % CHANGE vs. SUPPLY VOLTAGE
DS 1089L toc05
FREQUENCY % CHANGE vs. TEMPERATURE
VCC = 3.3V
DS 1089L toc06
5 VCC = 3.3V, PDN = GND 4 SUPPLY CURRENT (A)
0.50 TA = +25C FREQUENCY CHANGE (%) 0.25 66MHz 0 130kHz 33MHz
0.2
FREQUENCY CHANGE (%)
0 130kHz -0.2
3
2
-0.4 50MHz 66MHz -0.6 33MHz
-0.25 50MHz
1
0 -40 -15 10 35 60 85 TEMPERATURE (C)
-0.50 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
-0.8 -40 -15 10 35 60 85 TEMPERATURE (C)
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5
3.3V Center Spread-Spectrum EconOscillatorTM DS1089L
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
DUTY CYCLE vs. SUPPLY VOLTAGE
DS 1089L toc07
DUTY CYCLE vs. TEMPERATURE
DS 1089L toc08
SPECTRUM COMPARISON (120kHz BW, SAMPLE DETECT)
-10 POWER SPECTRUM (dBm) -20 -30 -40 -50 -60 -70 4% 8% 2% 1% NO SPREAD
DS 1089L toc09
58
TA = +25C 66MHz 50MHz 33MHz
58 VCC = 3.3V 56 66MHz DUTY CYCLE (%) 54 50MHz
0
56 DUTY CYCLE (%)
54
52
52 33MHz
50 130kHz 48 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
50 130kHz 48 -40 -15 10 35 60 85 TEMPERATURE (C)
-80 -90 44 46
fMOSC = 50MHz, DITHER RATE = fMOSC / 4096 48 50 52 54 56
FREQUENCY (MHz)
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME OUT SPRD VCC GND OE PDN SDA SCL Oscillator Output Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled. Power Supply Ground Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is disabled but the internal master oscillator is still on. Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master oscillator and the output buffer are disabled (power-down mode). I2C Serial Data. This pin is for serial data transfer to and from the device. I2C Serial Clock. This pin is used to clock data into and out of the device. FUNCTION
6
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3.3V Center Spread-Spectrum EconOscillatorTM
Block Diagram
DS1089L
PDN OE SDA I2C I2C SERIAL ADDRESS INTERFACE BITS SCL ADDR J3 WRITE EE COMMAND EEPROM WRITE CONTROL EEPROM DITHER RATE DITHER % VCC VCC GND PRESCALER LO/ HIZ TRIANGLEWAVE GENERATOR fMOSC J2 OE X WC A2 A1 A0 FACTORYPROGRAMMED MASTER OSCILLATOR 33.3MHz TO 66.6MHz f MOD PRESCALER fMOSC DIVIDE BY 1, 2, 4, 8, 16, 32, 64, 128, OR 256 fOSC SYNCED OUTPUT BUFFER fOUT OUT H/W GATED OUTPUT
DS1089L
CONTROL REGISTERS S/W GATED OUTPUT OUTPUT CONTROL
J1
J0
X
P3
P2
P1
P0 PRESCALER SETTING OUTPUT CONFIGURATION
SPRD
Detailed Description
Master Oscillator
The internal master oscillator is capable of generating a square wave with a 33.3MHz to 66.6MHz frequency range. The master oscillator frequency (fMOSC) is factory programmed, and is specified in the Ordering Information.
Table 1. Prescaler Divider Settings
BITS P3, P2, P1, P0 0000 0001 0010 0011 0100 0101 0110 0111 1000 2x = 1 2 4 8 16 32 64 128 256 fOUT = fOSC fMOSC fMOSC / 2 fMOSC / 4 fMOSC / 8 fMOSC / 16 fMOSC / 32 fMOSC / 64 fMOSC / 128 fMOSC / 256
Prescaler
The user can program the prescaler divider to produce an output frequency (fOUT) as low as 130kHz using bits P0, P1, P2, and P3 in the PRESCALER register. The output frequency can be calculated using Equation 1. Any value programmed greater than 28 will be decoded as 28. See Table 1 for prescaler divider settings. Equation 1 f Output Frequency (Hz) fOSC = MOSC 2x where x = P3, P2, P1, P0
1111
256
fMOSC / 256
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7
3.3V Center Spread-Spectrum EconOscillatorTM DS1089L
Output Control
Two user control signals control the output. The output enable pin (OE) gates the output buffer and the powerdown pin (PDN) disables the master oscillator and turns off the output for power-sensitive applications. (Note: the power-down command must persist for at least two output frequency cycles plus 10s for deglitching purposes.) On power-up, the output is disabled until power is stable and the master oscillator has generated 512 clock cycles. Additionally, the OE input is OR'ed with the OE bit in the ADDR register, allowing for either hardware or software gating of the output waveform (see the Block Diagram). Both controls feature a synchronous enable, which ensures that there are no output glitches when the output is enabled. The synchronous enable also ensures a constant time interval (for a given frequency setting) from an enable signal to the first output transition.
Dither Percentage Settings
The dither amplitude (measured in percentage of the master oscillator center frequency) is set using the J2 and J3 bits in the ADDR register. This circuit uses a sense current from the master oscillator bias circuit to adjust the amplitude of the triangle-wave signal to a voltage level that modulates the master oscillator to a percentage of its factory-programmed center frequency. This percentage is set in the application to be 1%, 2%, 4%, or 8% (see Table 3). The location of bits P3, P2, P1, P0, J1, and J0 in the PRESCALER register and bits J3 and J2 in the ADDR register are shown in the Register Summary section.
Table 2. Dither Frequency Settings
BITS J1, J0 00 01 10 11 DITHER FREQUENCY No dither fMOSC / 2048 fMOSC / 4096 fMOSC / 8192
Dither Generator
The DS1089L has the ability to reduce radiated emission peaks. The output frequency can be dithered by 1%, 2%, 4%, or 8% symmetrically around the programmed center frequency. Although the output frequency changes when the dither is enabled, the duty cycle does not change. The dither rate (fMOD) is controlled by the J0 and J1 bits in the PRESCALER register and is enabled with the SPRD pin. The maximum spectral attenuation occurs when the prescaler is set to 1. The spectral attenuation is reduced by 2.7dB for every factor of 2 that is used in the prescaler. This happens because the prescaler's divider function tends to average the dither in creating the lower frequency. However, the most stringent spectral emission limits are imposed on the higher frequencies where the prescaler is set to a low divider ratio. A triangle-wave generator injects an offset element into the master oscillator to dither its output. The dither rate can be calculated based on the master oscillator frequency (see Equation 2). Equation 2 f fMOD = MOSC n where fMOD = dither frequency, fMOSC = master oscillator frequency, and n = divider setting (see Table 2).
Table 3. Dither Percentage Settings
BITS J3, J2 00 01 10 11 DITHER AMOUNT 1% 2% 4% 8%
8
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3.3V Center Spread-Spectrum EconOscillatorTM
When dither is enabled (by selecting a dither frequency setting greater than 0 with SPRD high), the master oscillator frequency is dithered around the center frequency by the selected percentage from the programmed fMOSC (see Figure 2). For example, if fMOSC is programmed to 40MHz (factory setting) and the dither amount is programmed to 1%, the frequency of fMOSC will dither between 39.6MHz and 40.4MHz at a modulation frequency determined by the selected dither frequency. Continuing with the same example, if J1 = 0 and J0 = 1, selecting fMOSC / 2048, then the dither frequency would be 19.531kHz.
DS1089L
IF DITHER AMOUNT = 0% (+1, 2, 4, OR 8% OF fMOSC) PROGRAMMED fMOSC (-1, 2, 4, OR 8% OF fMOSC) fMOSC DITHER AMOUNT (2, 4, 8, OR 16%)
1 fMOD
Register Summary
The DS1089L registers are used to change the dither amount, output frequency, and slave address. A bit summary of the registers is shown in Table 4. Once programmed into EEPROM, the settings only need to be reprogrammed if it is desired to reconfigure the device.
TIME
Figure 2. Output Frequency vs. Dither Rate
PRESCALER Register
Bits 7 to 6: Dither Frequency. The J1 and J0 bits control the dither frequency applied to the output. See Table 2 for divider settings. If either of bits J1 or J0 is high and SPRD is high, dither is enabled. Output Low or Hi-Z. The LO/HIZ bit determines the state of the output during power-down. While the output is deactivated, if the LO/HIZ bit is set to 0, the output will be high impedance (high-Z). If the LO/HIZ bit is set to 1, the output will be driven low. Reserved. Prescaler Divider. The prescaler bits (bits P3 to P0) divide the master oscillator frequency by 2x where x can be from 0 to 8. Any prescaler bit value entered that is greater than 8 will decode as 8. See Table 1 for prescaler settings.
ADDR Register
Bits 7 to 6: Dither Percentage. The J3 and J2 bits control the selected dither amplitude (%). When both J3 and J2 are set to 0, the default dither rate is 1%. Output Enable. The OE bit and the OE pin state determine if the output is on when the device is active (PDN = VIH). If (OE = 0 OR OE is high) AND the PDN pin is high, the output will be driven. Reserved. Write Control. The WC bit determines if the EEPROM is to be written after register contents have been changed. If WC = 0 (default), EEPROM is written automatically after a write. If WC = 1, the EEPROM is only written when the WRITE EE command is issued. See the WRITE EE Command section for more information. Address. The A0, A1, A2 bits determine the lower nibble of the I2C slave address.
Bit 5:
Bit 5:
Bit 4: Bit 3:
Bit 4: Bits 3 to 0:
Bits 2 to 0:
Table 4. Register Summary
REGISTER PRESCALER ADDR WRITE EE ADDR 02h 0Dh 3Fh BIT7 J1 J3 J0 J2 LO/ HIZ OE BINARY X X P3 WC P2 A2 P1 A1 BIT0 P0 A0 DEFAULT xx00xxxxb xx100000b -- ACCESS R/W R/W --
No Data
X = "don't care" x = values depend on custom settings _____________________________________________________________________ 9
3.3V Center Spread-Spectrum EconOscillatorTM DS1089L
WRITE EE Command
The WRITE EE command is useful in closed-loop applications where the registers are frequently written. In applications where the register contents are frequently written, the WC bit should be set to 1 to prevent wearing out the EEPROM. Regardless of the value of the WC bit, the value of the ADDR register is always written immediately to EEPROM. When the WRITE EE command has been received, the contents of the registers are written into the EEPROM, thus locking in the register settings.
I2C Serial Port Operation
SDA
MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 START CONDITION 2 6 7 8 9 ACK REPEATED IF MORE BYTES ARE TRANSFERRED 1 2 3-7 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
Figure 3. I2C Data Transfer Protocol
MSB 1 0 1 1 A2 A1 DEVICE ADDRESS A0
LSB R/W
DEVICE IDENTIFIER
READ/WRITE BIT
Figure 4. Slave Address Byte
10
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3.3V Center Spread-Spectrum EconOscillatorTM DS1089L
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure 5. I2C AC Characteristics
TYPICAL I2C WRITE TRANSACTION MSB START 1 0 1 1 LSB A2* A1* A0* R/W DEVICE ADDRESS READ/ WRITE SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
DEVICE IDENTIFIER
COMMAND/REGISTER ADDRESS
DATA
EXAMPLE I2C TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO) B0h 02h DATA SLAVE SLAVE A) SINGLE BYTE WRITE 10000000 START 1 0 1 1 0 0 0 0 ACK 0 0 0 0 0 0 1 0 ACK -WRITE PRESCALER REGISTER TO 128 B0h B) SINGLE BYTE READ -READ PRESCALER REGISTER START 1 0 1 1 0 0 0 0 02h SLAVE SLAVE 00000010 ACK ACK REPEATED START
SLAVE ACK B1h
STOP
10110001
DATA MASTER SLAVE 10000000 NACK ACK
STOP
*THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST MATCH THE ADDRESS SET IN THE ADDR REGISTER.
Figure 6. I2C Transactions
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS1089L, decouple the power supply with 0.01F and 0.1F high-quality, ceramic, surface-mount capacitors. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors
tend to have adequate high-frequency response for decoupling applications. These capacitors should be placed as close to the VCC and GND pins as possible.
Stand-Alone Mode
SCL and SDA cannot be left floating even in standalone mode. If the DS1089L will never need to be programmed in-circuit, including during production testing, SDA and SCL can be connected high.
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11
3.3V Center Spread-Spectrum EconOscillatorTM DS1089L
Typical Operating Circuits
PROCESSOR-CONTROLLED MODE
VCC
STAND-ALONE MODE
DITHERED 130kHz TO 66.6MHz OUTPUT OUT VCC SPRD
4.7k SCL
4.7k
DITHERED 130kHz TO 66.6MHz OUTPUT XTL1/OSC1 VCC XTL2/OSC2 MICROPROCESSOR VCC PDN N.C. SPRD OUT SCL*
VCC
2-WIRE INTERFACE VCC
DS1089L
SDA
DS1089L SDA*
VCC
PDN
GND
OE
GND
OE
DECOUPLING CAPACITORS (0.1F and 0.01F)
DECOUPLING CAPACITORS (0.1F and 0.01F) *SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1089L NEVER NEEDS TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING.
Pin Configuration
TOP VIEW
Chip Topology
TRANSISTOR COUNT: 5985 SUBSTRATE CONNECTED TO GROUND
OUT 1 SPRD 2
8 SCL 7 SDA
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
DS1089L
VCC 3 GND 4 6 PDN 5 OE
SOP (118 mils)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
is a registered trademark of Dallas Semiconductor Corporation.

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